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2007-10-06

 

NWCPP: Herb Sutter - Things Your Programming Language Never Told You

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Living a short commute from Redmond, Washington, I was able to attend the Northwest C++ group's meeting with Herb Sutter on September 19.   I was delighted to have my Herb Sutter books autographed.  I follow Sutter's blog, so his name has high recognition for me, more than for his being Chair of the ISO committee on C++.   Andrei Alexandrescu, co-author of C++ Coding Standards: 101 Rules, Guidelines, and Best Practices was also at the standing-room-only presentation.  He signed my book as well.  Not being a Dr. Dobb's regular, I didn't know much about Alexandrescu and I hope we'll see more of him as he completes his graduate studies.

The talk centered on machine architectures and how that impacts the optimization of programs (by compilers) and the performance of the code that we write, performance that we may have little sense for.  Sutter has announced the video and slide set for your viewing.  This will completely shatter many ideas about how to write "optimum" programs and whether one should even try (although reducing algorithmic complexity (and decision cost) is almost always a good idea, as reinforced near the end of the talk:

Herb Sutter: Suggestions for "Required Viewing": Machine Architecture Talk OnlineSutter's Mill (web log), 2007-09-24.  The video is a little low-resolution, but having the discussion and verbal presentation is invaluable.  I recommend having the slides open so that you can follow along with the talk in the video.

Here's my skimpy collection of bullet points, but a review of the slides and an index to the now-available video would be superior:

  • Latency is the root of all complexity 2007-09-19 NWCPP: Timothy Knox and Herb Sutter Stand-Up
  • Assembler: you know what the line of code does, you know how long it takes.
  • Does it affect my code's performance?
  • Bandwidth vs. Latency
  • You can always solve a bandwidth problem with money.
  • Don't count on buying your way out of a latency problem.
  • Everything about the complexity of hardware performance improvement has been true for past 40 years.
  • Actual Memory Hierarchy reviewed (simplified)
  • DRAM latency is ~200 clocks.  ("DRAM bad!")
  • Little's Law: Bandwidth X Latency = Concurrency
  • data caching & store caching can effect your code.(concurrency)
  • pipeline execution impacts code
  • Modern CPU chip: 85% cache, 99% to move/store data [and we once thought 15% operating-system overhead was a bad deal]
  • The memory hierarchy is just going to get deeper. 2007-09-19 NWCPP: Taking the Sutter Pledge
  • l979 Lamport - Sequential consistency.
  • All the things that can perturb the actual execution.  Rearrangements are OK if you can never tell the difference (apart from performance improvement).
  • Must not have "gray bits" that are controlled on a different critical section [related to problem of leaks that breach invariants for safe concurrency, but I forget the illustration now].
  • Interesting question about a suspect sequence of operations that appears to be safe and isn't.
  • Performance: Is it faster to sum an array of ints, a list of ints, or a tree of some sort?
  • Intel Rightmark [?] Analyzer providing interesting results

Fortunately, the slides of the presentation have been made available and you can figure it out from there.

[update 2007-10-08: Added the link to the video of Sutter's presentation and his recommendation about this particular topic.  I also remember talking to someone near the door afterward and remarking that computer processors are like software now, not because of micro-programming but because of the scheduling and heuristics for pipelining and maintaining consistency.  Now the compiler doesn't reorder your code (though it can help the processor that way), the processor reorders and interleaves your code to hide latency in concurrency.  There was a recent blog post that reminded me of that.  I'll find it again eventually.]

 
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